+llXd x/ت <( 2\Ffq{Q0>KYgt B0Vk~ />N^lz%7GYu$2?KXet always assign automatic begin case casex casez cell config deassign default defparam design disable edge elseend endcase endconfig endgenerate endmodule endfunction endprimitive endspecify endtable endtask eventfor force forever fork function generate genvarif ifnone incdir include initial inout input instance join liblist library localparam macromodule module negedgenoshowcancelled output parameter posedge primitivepulsestyle_ondetectpulsestyle_oneventreg release repeat scalared showcancelled signed specify specparam strength table tasktri tri0 tri1 triand trior wandwor trireg unsigneduse vectored wait while wire+-!~*/%<<>><<=>>====!====!==&~&^^~|~|&&||?:Verilog Custom1_$ d xtd h d d R d pqd +T?g'"module\w+\([a-zA-Z][a-zA-Z0-9_]*\)% task\w+\([a-zA-Z][a-zA-Z0-9_]*\)2-function\w+\[.*\]\w+\([a-zA-Z][a-zA-Z0-9_]*\)'"begin:\w+\([a-zA-Z][a-zA-Z0-9_]*\)&!input\w+\([a-zA-Z][a-zA-Z0-9_]*\)/*input\w+\[.*\]\w+\([a-zA-Z][a-zA-Z0-9_]*\))$function\w+\([a-zA-Z][a-zA-Z0-9_]*\)$reg\w+\([a-zA-Z][a-zA-Z0-9_]*\)-(reg\w+\[.*\]\w+\([a-zA-Z][a-zA-Z0-9_]*\).)wire\w+\[.*\]\w+\([a-zA-Z][a-zA-Z0-9_]*\)% wire\w+\([a-zA-Z][a-zA-Z0-9_]*\)'"output\w+\([a-zA-Z][a-zA-Z0-9_]*\)0+output\w+\[.*\]\w+\([a-zA-Z][a-zA-Z0-9_]*\)L@ d @a @}//Comment Single LineA~/**/Comment Multi LineA""\String Single Line